Efficient Modified Reduced FFT(MRFFT) Feedback-Commutator Architecture Design

International Journal of VLSI & Signal Processing

© 2019 by SSRG - IJVSP Journal

Volume 6 Issue 1

Year of Publication : 2019

Authors : P.Kabilamani, Dr.C.Gomathy

10.14445/23942584/IJVSP-V6I1P101

How to Cite?

P.Kabilamani, Dr.C.Gomathy, "Efficient Modified Reduced FFT(MRFFT) Feedback-Commutator Architecture Design," SSRG International Journal of VLSI & Signal Processing, vol. 6,  no. 1, pp. 1-4, 2019. Crossref, https://doi.org/10.14445/23942584/IJVSP-V6I1P101

Abstract:

In this paper, an efficient MRFFT has been proposed by combining the characteristics of each Radix-2 single delay feedback (R2SDF) and Radix-4 multipath delay commutator (R4MDC).The MRFFT design uses commutator rather than advanced multipliers which reduces latency and the usage of processing elements is reduced which in turn reduces the hardware complexity. In future, the MRFFT design can be used to improve the performances of LTE wireless communication mainly for low coverage area where the signal strength is low. The proposed MRFFT is implemented by using verilog and verified by using modelsim.

Keywords:

MRFFT, Radix-4 multipath delay commutator, Radix-2 single delay feedback,OFDM.

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