Comparison between the performance of the Simulated Annealing and Genetic Algorithms in Physical Conductor Orientation within FPGA

International Journal of VLSI & Signal Processing

© 2019 by SSRG - IJVSP Journal

Volume 6 Issue 3

Year of Publication : 2019

Authors : Roba khega, Kamal Mahmoud Afisa, Mohammed Yassin Subaih

10.14445/23942584/IJVSP-V6I3P104

How to Cite?

Roba khega, Kamal Mahmoud Afisa, Mohammed Yassin Subaih, "Comparison between the performance of the Simulated Annealing and Genetic Algorithms in Physical Conductor Orientation within FPGA," SSRG International Journal of VLSI & Signal Processing, vol. 6,  no. 3, pp. 14-17, 2019. Crossref, https://doi.org/10.14445/23942584/IJVSP-V6I3P104

Abstract:

Reducing the number and length of physical conductors is an important aspect of circuit design, and is the core of systems using SOC (System on Chip) technology. The research presents a comparison between the performance of the Genetic Algorithms and the Simulated Annealing algorithm in the process of arranging the elements and paths of electronic circuits used in the chip (Field Programmable Gate Array FPGA). The research presents the most important points of comparison and guidance criteria for each of the two algorithms in terms of the number of conductors and processing time.

Keywords:

FPGA، Simulated Annealing, Genetic Algorithms

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