Design of Programmable High Speed I/O S
| International Journal of VLSI & Signal Processing |
| © 2019 by SSRG - IJVSP Journal |
| Volume 6 Issue 3 |
| Year of Publication : 2019 |
| Authors : Aruna Rao B P, Shanthi Prasad M J |
10.14445/23942584/IJVSP-V6I3P105
How to Cite?
Aruna Rao B P, Shanthi Prasad M J, "Design of Programmable High Speed I/O S," SSRG International Journal of VLSI & Signal Processing, vol. 6, no. 3, pp. 18-22, 2019. Crossref, https://doi.org/10.14445/23942584/IJVSP-V6I3P105
Abstract:
In this paper an attempt is made to design some basic features of a programmable high speed I/O like bidirectionality of I/Os, buffering of I/Os and supporting different voltage levels with the help of cadence tool, Incisive Simulator v (NC-SIM)
Keywords:
high speed I/O, bidirectionality of I/Os, buffering of I/Os, cadence, Incisive Simulator
References:
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