Reduced Power Using Grouping of Flip - Flop Sequential Instruction Pipe Lining

International Journal of VLSI & Signal Processing

© 2020 by SSRG - IJVSP Journal

Volume 7 Issue 1

Year of Publication : 2020

Authors : Bhumika Chaurasia, Nishi Pandey, Meha Shrivastava

10.14445/23942584/IJVSP-V7I1P101

How to Cite?

Bhumika Chaurasia, Nishi Pandey, Meha Shrivastava, "Reduced Power Using Grouping of Flip - Flop Sequential Instruction Pipe Lining," SSRG International Journal of VLSI & Signal Processing, vol. 7,  no. 1, pp. 1-5, 2020. Crossref, https://doi.org/10.14445/23942584/IJVSP-V7I1P101

Abstract:

The data will be received with the help of clock pulses that reduce the total energy consumption of digital electronic chips [1]-[6]. Driven data is causing area and power overhead that must be considered to minimize the impact of overhead. Therefore, this group is beneficial for FFs whose switching activities are highly correlated and elicit a combined enable signal [7]-[12]. Clock power is the main contributor to dynamic power for the modern design of integrated circuits. Expert work clock synchronization is a surprisingly effective technique for reducing the dynamic competition of sitting outside the rig timing subsystem. This article illustrates the clock activation strategies considered by several testers [13]-[17]. It shows the plane of the encoder and decoder sections of the correspondence structure with a clock arrangement to advance the power without destroying the execution of the function. The extension of the clock activation control required with novel parts of a pair of circuits is less intended by some professionals. A strategy-initiated flip-tumble (PTFF) with adaptive pulse is presented. The work illustrates the properties of PTFF in the rationalization of the control of components and the energy solution, which causes an improved control figure [18]-[24]. Manufacturers minimized HSPICE by light by 51% using an accelerator for channelling the clock loop of the binary clock trace door in the attached file.

Keywords:

clock synchronization (CG), clock network synthesis, low power design, multi bit flip-flop (MBFF), power estimator, DFD and RDFD

References:

[1] Shmuelwimer and Israel Koren “Design Flow For Flip-Flop Grouping In Data-Driven Clock Gating”, Ieee, 2014, Pp 771-778.
[2] A. Rangana Yakulu and K. Satya Prasad “Low Power Correlator Using Signal Range And Sub Word Based Clock Gating Scheme”, International Journal Of Hybrid Information Technology, 2016, Pp 159-170.
[3] T.Naresh And M.Lakshmikiran “Power Reduction With Flip Flop Grouping In Data Driven Clock Gating”, International Journal Of Engineering And Computer Science, 2015, Pp 11835-11838.
[4] Dushyant Kumar Soni And Ashishhiradhar “Dynamic Power Reduction Of Synchronous Digital Design By Using Of Efficient Clock Gating Technique”, International Journal Of Engineering And Techniques, 2015, Pp 18-23.
[5] Vidya K And Mr R. Karthik “A Look Ahead Partial Bus Specific Clock Gating Based On Autogated Flipflops”, International Journal Of Research In Science And Engineering, 2015, Pp 1-7.
[6] Saurabhkshirsagar And Dr. M B Mali “Data Driven Clock Gating For Logical Groups In Low Power Applications”, Ijesc, 2015, Pp 1454-1457.
[7] Renukajaiswal, Ranbir Paul And Vikasranjanmahto “Power Reduction In Cmos Technology By Using Tri-State Buffer And Clock Gating”, Ijarcet, 2014, Pp 1853-1860.
[8] R Dhivyabharathi And M Sunil Karthik “A Pass Transistor Based D Flip-Flop Design Using Negative Edge Triggered Circuit”, Ijerst, 2015, Pp 63-69.
[9] S Chindhu And S Thenappan “Pass Transistor Based Conventional Data Flip Flop Design”, Ijerst, 2015, Pp 278-284.
[10] Kakarlasandhya Rani And Krishna Prasad Satamraju “A Novel Approach For Auto Clock Gating Of Flip-Flops”, Ijser, 2015, Pp 132-136.
[11] Anujaaravind And Raseena K.A “Design Of An Alu With A Low Power Lfsr Using Clock Gating”, Ijsetr, 2014, Pp 2636-2639.
[12] Abhishekmashetty, Rajashekar Reddy Merugu, Sanjay Dubey And Vejandla Vijay Bhaskar “Data Driven Clock Gating Technique For Dynamic Power Reduction In Digital Design”, Journal Of Chemical And Pharmaceutical Sciences, 2016, Pp 511-514.
[13] C.Subin Raj, S.Jebasingkirubakaran And P.Balavengateswarlu “Look Ahead Clock Gating Using An Auto Gated Flip Flop For Low Power Application”, Journal Of Chemical And Pharmaceutical Sciences, 2016, Pp 969-973.
[14] D.Nirosha And T.Thangam “Design And Implementation Of 32 Bit Alu Using Look Ahead Clock Gating Logic”, Ijeter, 2016, Pp 101-104.
[15] Shmuelwimer And Aryealbahari “A Look-Ahead Clock Gating Based On Auto-Gated Flip-Flops”, Ieee, 2014, Pp 1465-1472.
[16] Mayuri B. Junghare And Aparna S. Shinde “A Clock Gating Technique Using Auto Gated Flip Flop For Look Ahead Clock Gating”, Ijsr, 2013, Pp 1525-1530.
[17] Zhengxu And Kenneth L. Shepard “Design And Analysis Of Actively-Deskewed Resonant Clock Networks”, IEEE, 2009, Pp 558-568.
[18] Jason H. Anderson And Farid N. “Power Estimation Techniques For Fpgas”, Ieee, 2004, Pp 1015-1027.
[19] D. Popa, Z. Sun, F. Torrisi, T. Hasan, F. Wang And A. C. Ferrari “Sub 200fs Pulse Generation From A Graphene Mode-Locked fiber Laser”, Ieee, 2010, Pp 1-3.
[20] Wimbogaerts, Shankar Kumar Selvaraja, Pieter Dumon, Joostbrouckaert, Katrien De Vos, Dries Van Thourhout And Roelbaets “Silicon-On-Insulator Spectral Filters Fabricated With Cmos Technology”, Ieee, 2010, Pp 33-44.
[21] Shmuel Wimer And Arye Albahari “A Look-Ahead Clock Gating Based On Auto-Gated Flip-Flops”, Ieee, 2014, Pp 1465-1475.
[22] Chaurasia B, Pandey N, Shrivastava M. A Review on Low Power Memory Design Technique. Int J VLSI Signal Process 2019;6:10–3. doi:10.14445/23942584/ijvsp-v6i3p103.
[23] Sharma A, Gupta DC. Modified radix 12 Multiplier for reducing area of designed circuit with reduce time delay. Int J VLSI Signal Process 2019;6:6–9. doi:10.14445/23942584/ijvsp-v6i3p102.
[24] P ARB, J SPM. Design of Programmable High Speed I / O S 2019;6:18–22.